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3 Volt Intel(R) StrataFlashTM Memory
28F128J3A, 28F640J3A, 28F320J3A (x8/x16)
Preliminary Datasheet
Product Features
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High-Density Symmetrically-Blocked Architecture -- 128 128-Kbyte Erase Blocks (128 M) -- 64 128-Kbyte Erase Blocks (64 M) -- 32 128-Kbyte Erase Blocks (32 M) High Performance Interface Asynchronous Page Mode Reads -- 110/25 ns Read Access Time (32 M) -- 120/25 ns Read Access Time (64 M) -- 150/25 ns Read Access Time (128 M) 2.7 V-3.6 V VCC Operation 128-bit Protection Register -- 64-bit Unique Device Identifier -- 64-bit User Programmable OTP Cells Enhanced Data Protection Features Absolute Protection with VPEN = GND -- Flexible Block Locking -- Block Erase/Program Lockout during Power Transitions
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Packaging -- 56-Lead TSOP Package -- 64-Ball Intel(R) Easy BGA Package Cross-Compatible Command Support Intel Basic Command Set -- Common Flash Interface -- Scalable Command Set 32-Byte Write Buffer -- 6 s per Byte Effective Programming Time 12.8M Total Min. Erase Cycles (128 Mbit) 6.4M Total Min. Erase Cycles (64 Mbit) 3.2M Total Min. Erase Cycles (32 Mbit) -- 100K Minimum Erase Cycles per Block Automation Suspend Options -- Block Erase Suspend to Read -- Block Erase Suspend to Program -- Program Suspend to Read 0.25 Intel(R) StrataFlashTM Memory Technology
Capitalizing on Intel's 0.25 generation two-bit-per-cell technology, second generation Intel(R) StrataFlashTM memory products provide 2X the bits in 1X the space, with new features for mainstream performance. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, these devices bring reliable, two-bit-per-cell storage technology to the flash market segment. Benefits include: more density in less space, high-speed interface, lowest cost-per-bit NOR devices, support for code and data storage, and easy migration to future devices. Using the same NOR-based ETOXTM technology as Intel's one-bit-per-cell products, Intel StrataFlash memory devices take advantage of over one billion units of manufacturing experience since 1987. As a result, Intel StrataFlash components are ideal for code and data applications where high density and low cost are required. Examples include networking, telecommunications, digital set top boxes, audio recording, and digital imaging. By applying FlashFileTM memory family pinouts, Intel StrataFlash memory components allow easy design migrations from existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation Intel StrataFlash memory (28F640J5 and 28F320J5) devices. Intel StrataFlash memory components deliver a new generation of forward-compatible software support. By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices. Manufactured on Intel(R) 0.25 micron ETOXTM VI process technology, Intel StrataFlash memory provides the highest levels of quality and reliability.
Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 290667-008 www..com April 2001
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Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 28F128J3A, 28F640J3A, 28F320J3A may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 1999-2001 *Other names and brands may be claimed as the property of others.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Contents
1.0 2.0 3.0 Product Overview.......................................................................................................1 Principles of Operation............................................................................................6
2.1 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Data Protection...................................................................................................... 6 Read...................................................................................................................... 8 Output Disable....................................................................................................... 8 Standby ................................................................................................................. 8 Reset/Power-Down ............................................................................................... 8 Read Query ........................................................................................................... 9 Read Identifier Codes............................................................................................ 9 Write ...................................................................................................................... 9 Read Array Command.........................................................................................13 Read Query Mode Command .............................................................................13 4.2.1 Query Structure Output ..........................................................................13 4.2.2 Query Structure Overview ......................................................................14 4.2.3 Block Status Register .............................................................................15 4.2.4 CFI Query Identification String ...............................................................15 4.2.5 System Interface Information .................................................................16 4.2.6 Device Geometry Definition....................................................................17 4.2.7 Primary-Vendor Specific Extended Query Table....................................18 Read Identifier Codes Command ........................................................................19 Read Status Register Command.........................................................................20 Clear Status Register Command.........................................................................22 Block Erase Command........................................................................................22 Block Erase Suspend Command ........................................................................22 Write to Buffer Command....................................................................................23 Byte/Word Program Commands .........................................................................24 Program Suspend Command..............................................................................24 Set Read Configuration Command .....................................................................24 4.11.1 Read Configuration ................................................................................25 Configuration Command .....................................................................................25 Set Block Lock-Bit Commands............................................................................26 Clear Block Lock-Bits Command.........................................................................27 Protection Register Program Command .............................................................27 4.15.1 Reading the Protection Register ............................................................27 4.15.2 Programming the Protection Register ....................................................27 4.15.3 Locking the Protection Register .............................................................28 Three-Line Output Control...................................................................................38 STS and Block Erase, Program, and Lock-Bit Configuration Polling ..................38 Power Supply Decoupling ...................................................................................38 Input Signal Transitions - Reducing Overshoots and Undershoots When Using
Bus Operations ........................................................................................................... 7
4.0
Command Definitions...............................................................................................9
4.1 4.2
4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15
5.0
Design Considerations ..........................................................................................38
5.1 5.2 5.3 5.4
Preliminary
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28F128J3A, 28F640J3A, 28F320J3A
5.5 5.6 5.7
Buffers or Transceivers39 VCC, VPEN, RP# Transitions ............................................................................. 39 Power-Up/Down Protection................................................................................. 39 Power Dissipation ............................................................................................... 40 Absolute Maximum Ratings ................................................................................ 40 Operating Conditions .......................................................................................... 41 Capacitance ........................................................................................................ 41 DC Characteristics .............................................................................................. 42 AC Characteristics-- Read-Only Operations(1,2)................................................. 45 AC Characteristics-- Write Operations(1,2) ......................................................... 47 Block Erase, Program, and Lock-Bit Configuration Performance(1,2,3) ............... 48
6.0
Electrical Specifications........................................................................................ 40
6.1 6.2 6.3 6.4 6.5 6.6 6.7
7.0 8.0
Ordering Information .............................................................................................. 51 Additional Information ........................................................................................... 52
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28F128J3A, 28F640J3A, 28F320J3A
Revision History
Date of Revision 07/07/99 08/03/99 09/07/99 12/16/99 Version -001 -002 -003 -004 Original Version A0-A2 indicated on block diagram Changed Minimum Block Erase time,IOL, IOH, Page Mode and Byte Mode currents. Modified RP# on AC Waveform for Write Operations Changed Block Erase time and tAVWH Removed all references to 5 V I/O operation Corrected Ordering Information, Valid Combinations entries Changed Min program time to 211 s Added DU to Lead Descriptions table Changed Chip Scale Package to Ball Grid Array Package Changed default read mode to page mode Removed erase queuing from Figure 10, Block Erase Flowchart Added Program Max time Added Erase Max time Added Max page mode read current Moved tables to correspond with sections Fixed typographical errors in ordering information and DC parameter table Removed VCCQ1 setting and changed VCCQ2/3 to VCCQ1/2 Added recommended resister value for STS pin Change operation temperature range Removed note that rp# could go to 14 V Removed VOL of 0.45 V Removed VOH of 2.4 V Updated ICCR Typ values Added Max lock-bit program and lock times Added note on max measurements Updated cover sheet statement of 700 million units to one billion. Corrected Table 10 to show correct maximum program times. Corrected error in Max block program time in section 6.7 Corrected typical erase time in section 6.7 Updated cover page to reflect 100K minimum erase cycles. Updated cover page to reflect 110 ns 32M read speed. Removed Set Read Configuration command from Table 4. Updated Table 8 to reflect reserved bits are 1-7; not 2-7. Updated Table 16 bit 2 definition from R to PSS. Changed VPENLK Max voltage from 0.8 V to 2.0 V, Section 6.4, DC Characteristics Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Section 6.5, AC Characteristics-Read-Only Operations (1,2) Updated write parameter W13 (tWHRL) from 90 ns to 500 ns, Section 6.6, AC Characteristics-Write Operations Updated Max. Program Suspend Latency W16 (tWHRH1) from 30 to 75 s, Section 6.7, Block Erase, Program, and Lock-Bit Configuration Performance (1,2,3) Revised Section 7.0, Ordering Information Description
03/16/00
-005
06/26/00
-006
2/15/01
-007
04/13/01
-008
Preliminary
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28F128J3A, 28F640J3A, 28F320J3A
1.0
Product Overview
The 0.25 3 Volt Intel StrataFlash memory family contains high-density memories organized as 16 Mbytes or 8 Mwords (128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords (32-Mbit). These devices can be accessed as 8- or 16-bit words. The 128-Mbit device is organized as one-hundred-twenty-eight 128-Kbyte (131,072 bytes) erase blocks. The 64-Mbit device is organized as sixty-four 128-Kbyte erase blocks while the 32-Mbits device contains thirty-two 128-Kbyte erase blocks. Blocks are selectively and individually lockable and unlockable insystem. A 128-bit protection register has multiple uses, including unique flash device identification. The device's optimized architecture and interface dramatically increases read performance by supporting page-mode reads. This read mode is ideal for non-clock memory systems. A Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backwardcompatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. A block erase operation erases one of the device's 128-Kbyte blocks typically within one second-- independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or program data from any other block. Similarly, program suspend allows system software to suspend programming (byte/ word program and write-to-buffer operations) to read data or execute code from any other block that is not being suspended. Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming performance. By using the Write Buffer, data is programmed in buffer increments. This feature can improve system program performance more than 20 times over non-Write Buffer writes. Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations. Lock-bit configuration operations set and clear lock-bits (Set Block Lock-Bit and Clear Block Lock-Bits commands). The status register indicates when the WSM's block erase, program, or lock-bit configuration operation is finished. The STS (STATUS) output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status indication using STS minimizes both CPU overhead and system power consumption. When configured in level mode (default mode), it acts as a RY/ BY# pin. When low, STS indicates that the WSM is performing a block erase, program, or lock-bit configuration. STS-high indicates that the WSM is ready for a new command, block erase is
Preliminary
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28F128J3A, 28F640J3A, 28F320J3A
suspended (and programming is inactive), program is suspended, or the device is in reset/powerdown mode. Additionally, the configuration command allows the STS pin to be configured to pulse on completion of programming and/or block erases. Three CE pins are used to enable and disable the device. A unique CE logic design (see Table 2, "Chip Enable Truth Table" on page 7) reduces decoder logic typically required for multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4-chip miniature card or SIMM module. The BYTE# pin allows either x8 or x16 read/writes to the device. BYTE# at logic low selects 8-bit mode; address A0 selects between the low byte and high byte. BYTE# at logic high enables 16-bit operation; address A1 becomes the lowest order address and address A0 is not used (don't care). A device block diagram is shown in Figure 1 on page 2. When the device is disabled (see Table 2 on page 7) and the RP# pin is at VCC, the standby mode is enabled. When the RP# pin is at GND, a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. 3 Volt Intel StrataFlash memory devices are available in two package types. Both 56-lead TSOP (Thin Small Outline Package) and BGA (Ball Grid Array Package) support all offered densities. Figure 2 and Figure 3 show the pinouts. Figure 1. 3 Volt Intel(R) StrataFlashTM Memory Block Diagram
DQ0 - DQ15
VCCQ
Output Buffer
Input Buffer
Query Output Latch/Multiplexer Write Buffer Identifier Register Status Register Data Register
I/O Logic CE Logic
VCC BYTE# CE0 CE1 CE2 WE# OE# RP#
Command User Interface
A0- A 2
Multiplexer Data Comparator
32-Mbit: A 0- A 21 64-Mbit: A 0 - A22 128-Mbit: A 0 - A23
Y-Decoder Input Buffer
Y-Gating 32-Mbit: Thirty-two 64-Mbit: Sixty-four 128-Mbit: One-hundred twenty-eight 128-Kbyte Blocks Write State Machine Program/Erase Voltage Switch
STS VPEN VCC GND
Address Latch Address Counter
X-Decoder
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28F128J3A, 28F640J3A, 28F320J3A
Table 1.
Symbol A0
Lead Descriptions
Type INPUT Name and Function BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is high). ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are internally latched during a program cycle. 32-Mbit: A0-A21 64-Mbit: A0-A22 128-Mbit: A0-A23 LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands during Command User Interface (CUI) writes. Outputs array, query, identifier, or status data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. Outputs DQ6-DQ0 are also floated when the Write State Machine (WSM) is busy. Check SR.7 (status register bit 7) to determine WSM status. HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations. Outputs array, query, or identifier data in the appropriate read mode; not used for status register reads. Floated when the chip is de-selected, the outputs are disabled, or the WSM is busy. CHIP ENABLES: Activates the device's control logic, input buffers, decoders, and sense amplifiers. When the device is de-selected (see Table 2 on page 7), power reduces to standby levels. INPUT All timing specifications are the same for these three signals. Device selection occurs with the first edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the first edge of CE0, CE1, or CE2 that disables the device (see Table 2 on page 7). RESET/ POWER-DOWN: Resets internal automation and puts the device in power-down mode. RP#high enables normal operation. Exit from reset sets the device to read array mode. When driven low, RP# inhibits write operations which provides data protection during power transitions. OUTPUT ENABLE: Activates the device's outputs through the data buffers during a read cycle. OE# is active low. WRITE ENABLE: Controls writes to the Command User Interface, the Write Buffer, and array blocks. WE# is active low. Addresses and data are latched on the rising edge of the WE# pulse. STATUS: Indicates the status of the internal state machine. When configured in level mode (default mode), it acts as a RY/BY# pin. When configured in one of its pulse modes, it can pulse to indicate program and/or erase completion. For alternate configurations of the STATUS pin, see the Configurations command. Tie STS to VCCQ with a pull-up resistor. BYTE ENABLE: BYTE# low places the device in x8 mode. All data is then input or output on DQ0- DQ7, while DQ8-DQ15 float. Address A0 selects between the high and low byte. BYTE# high places the device in x16 mode, and turns off the A0 input buffer. Address A1 then becomes the lowest order address. ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or configuring lock-bits. With VPEN VPENLK, memory contents cannot be altered. DEVICE POWER SUPPLY: With VCC VLKO, all write attempts to the flash memory are inhibited. OUTPUT BUFFER POWER SUPPLY: This voltage controls the device's output voltages. To obtain output voltages compatible with system data bus voltages, connect VCCQ to the system supply voltage. GROUND: Do not float any ground pins. NO CONNECT: Lead is not internally connected; it may be driven or floated. DON'T USE: Do not drive ball to VIH or VIL, leave disconnected
A1-A23
INPUT
DQ0-DQ7
INPUT/ OUTPUT
DQ8- DQ15
INPUT/ OUTPUT
CE0, CE1, CE2
RP#
INPUT
OE# WE#
INPUT INPUT OPEN DRAIN OUTPUT
STS
BYTE#
INPUT
VPEN VCC VCCQ GND NC DU
INPUT SUPPLY OUTPUT BUFFER SUPPLY SUPPLY
Preliminary
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28F128J3A, 28F640J3A, 28F320J3A
Figure 2. 3 Volt Intel(R) StrataFlashTM Memory Easy BGA Package
1 A A1 B A2 C A3 D A4 E DQ8 DQ1 DQ9 DQ3 DQ4 DU DU DQ15 STS F DU OE# G A23(2) H CE2# DU VCC GND DQ13 GND DQ7 A24(3) A0 DQ2 VCCQ DQ5 DQ6 DQ14 WE# H A24(3) DQ7 GND DQ13 GND VCC DU CE2# WE# DQ14 DQ6 DQ5 VCCQ DQ2 A0 A23(2) OE# DU DU DQ12 DQ11 DQ10 DQ0 BYTE# F BYTE# DQ0 DQ10 DQ11 DQ12 G A5 A11 RP# DU DU A16 A17 E STS DQ15 DU DQ4 DQ3 DQ9 DQ1 DQ8 A7 A10 A12 A15 DU A20 A21 D A17 A16 DU DU RP# A11 A5 A4 GND A9 CE0# A14 DU A19 CE1# C A21 A20 DU A15 A12 A10 A7 A3 A6 A8 VPEN A13 VCC A18 A22(1) B CE1# A19 DU A14 CE0# A9 GND A2 2 3 4 5 6 7 8 A A22(1) A18 VCC A13 VPEN A8 A6 A1 8 7 6 5 4 3 2 1
Top View - Ball Side Down
Bottom View - Ball Side Up
32 Mbit, 64 Mbit and 128 Mbit: 10 x 13 x 1.2 mm 1.0 mm-ball pitch
0667-02
NOTES: 1. Address A22 is only valid on 64-Mbit densities and above, otherwise, it is a no connect (NC) 2. Address A23 is only valid on 128-Mbit densities and above, otherwise, it is a no connect (NC) 3. Address A24 is only valid on 256-Mbit densities and above, otherwise, it is a no connect (NC) 4. Don't Use (DU) pins refer to pins that should not be connected
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28F128J3A, 28F640J3A, 28F320J3A
Figure 3. 3 Volt Intel(R) StrataFlashTM Memory 56-Lead TSOP (32/64/128 Mbit) Offers an Easy Migration from the 32-Mbit Intel StrataFlash Component (28F320J5) or the 16-Mbit FlashFileTM Component (28F160S3)
3 Volt Intel StrataFlash Memory 32/64/128M A22(1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 3 Volt Intel StrataFlash Memory 32/64/128M A24(3)
28F160S3 NC CE1 NC A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1
28F320J5 NC CE1 A21 A20 A19 A18 A17 A16
28F320J5 NC WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCCQ GND DQ11 DQ3 DQ10 DQ2 VCC(4) DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC CE2
28F160S3 WP# WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC
VCC(4) A15 A14 A13 A12 CE0 VPEN RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1
CE1 A21 A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPEN RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1
Intel(R) StrataFlashTM Memory 56-Lead TSOP Standard Pinout 14 mm x 20 mm Top View
WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCCQ GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# A23(2) CE2
Highlights pinout changes
0667-03
NOTES: 1. A22 exists on 64-, 128- and 256-Mbit densities. On 32-Mbit densities this pin is a no-connect (NC). 2. A23 exists on 128-Mbit densities. On 32- and 64-Mbit densities this pin is a no-connect (NC). 3. A24 exists on 256-Mbit densities. On 32-, 64- and 128-Mbit densities this pin is a no-connect (NC). 4. VCC = 5 V 10% for the 28F640J5/28F320J5.
Preliminary
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28F128J3A, 28F640J3A, 28F320J3A
2.0
Principles of Operation
The Intel StrataFlash memory devices include an on-chip WSM to manage block erase, program, and lock-bit configuration functions. It allows for 100% TTL-level control inputs, fixed power supplies during block erasure, program, lock-bit configuration, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from reset/power-down mode (see Section 3.0, "Bus Operations" on page 7), the device defaults to read array mode. Manipulation of external memory control pins allows array read, standby, and output disable operations. Read array, status register, query, and identifier codes can be accessed through the CUI (Command User Interface) independent of the VPEN voltage. VPENH on VPEN enables successful block erasure, programming, and lock-bit configuration. All functions associated with altering memory contents--block erase, program, lock-bit configuration--are accessed via the CUI and verified through the status register. Commands are written using standard micro-processor write timings. The CUI contents serve as input to the WSM, which controls the block erase, program, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latched during program cycles. Interface software that initiates and polls progress of block erase, program, and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read or program data from/to any other block. Program suspend allows system software to suspend a program to read data from any other flash memory array location.
2.1
Data Protection
Depending on the application, the system designer may choose to make the VPEN switchable (available only when memory block erases, programs, or lock-bit configurations are required) or hardwired to VPENH. The device accommodates either design practice and encourages optimization of the processor-memory interface. When VPEN VPENLK, memory contents cannot be altered. The CUI's two-step block erase, byte/ word program, and lock-bit configuration command sequences provide protection from unwanted operations even when VPENH is applied to VPEN. All program functions are disabled when VCC is below the write lockout voltage VLKO or when RP# is VIL. The device's block locking capability provides additional protection from inadvertent code or data alteration by gating erase and program operations.
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28F128J3A, 28F640J3A, 28F320J3A
3.0
Bus Operations
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.
Figure 4. Memory Map
A [23-0]:128 Mbit A [22-0]: 64 Mbit A [21-0]: 32 Mbit
FFFFFF
A [23-1]: 128 Mbit A [22-1]: 64 Mbit A [21-1]: 32 Mbit
7FFFFF
128-Kbyte Block
FE0000
127 7F0000
64-Kword Block
127
7FFFFF
3FFFFF
128-Kbyte Block
7E0000
63 3F0000
64-Kword Block
63
128-Kbyte Block
3E0000
31 1F0000
64-Kword Block
31
03FFFF
01FFFF
128-Kbyte Block
020000 01FFFF
1 010000 00FFFF 0 000000
64-Kword Block 64-Kword Block
1 0
128-Kbyte Block
000000
Byte-Wide (x8) Mode
Word Wide (x16) Mode
Table 2.
Chip Enable Truth Table
CE2 VIL VIL VIL VIL VIH VIH VIH VIH CE1 VIL VIL VIH VIH VIL VIL VIH VIH CE0 VIL VIH VIL VIH VIL VIH VIL VIH DEVICE Enabled Disabled Disabled Disabled Enabled Enabled Enabled Disabled
NOTE: For single-chip applications, CE2 and CE1 can be strapped to GND.
Preliminary
32-Mbit
64-Mbit
3FFFFF
1FFFFF
128-Mbit
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28F128J3A, 28F640J3A, 28F320J3A
3.1
Read
Information can be read from any block, query, identifier codes, or status register independent of the VPEN voltage. Upon initial device power-up or after exit from reset/power-down mode, the device automatically resets to read array mode. Otherwise, write the appropriate read mode command (Read Array, Read Query, Read Identifier Codes, or Read Status Register) to the CUI. Six control pins dictate the data flow in and out of the component: CE0, CE1, CE2, OE#, WE#, and RP#. The device must be enabled (see Table 2, "Chip Enable Truth Table" on page 7), and OE# must be driven active to obtain data at the outputs. CE0, CE1, and CE2 are the device selection controls and, when enabled (see Table 2), select the memory device. OE# is the data output (DQ0-DQ15) control and, when active, drives the selected memory data onto the I/O bus. WE# must be at VIH. When reading information in read array mode, the device defaults to asynchronous page mode. This mode provides high data transfer rate for memory subsystems. In this state, data is internally read and stored in a high-speed page buffer. A2:0 addresses data in the page buffer. The page size is four words or eight bytes. Asynchronous word/byte mode is supported with no additional commands required.
3.2
Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0-DQ15 are placed in a high-impedance state.
3.3
Standby
CE0, CE1, and CE2 can disable the device (see Table 2) and place it in standby mode which substantially reduces device power consumption. DQ0-DQ15 outputs are placed in a highimpedance state independent of OE#. If deselected during block erase, program, or lock-bit configuration, the WSM continues functioning, and consuming active power until the operation completes.
3.4
Reset/Power-Down
RP# at VIL initiates the reset/power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and turns off numerous internal circuits. RP# must be held low for a minimum of tPLPH. Time tPHQV is required after return from reset mode until initial memory access outputs are valid. After this wakeup interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H. During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In default mode, STS transitions low and remains low for a maximum time of tPLPH + tPHRH until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written.
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Preliminary
28F128J3A, 28F640J3A, 28F320J3A
As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, program, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper initialization may not occur because the flash memory may be providing status information instead of array data. Intel(R) Flash memories allow proper initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.
3.5
Read Query
The read query operation outputs block status information, CFI (Common Flash Interface) ID string, system interface information, device geometry information, and Intel-specific extended query information.
3.6
Read Identifier Codes
The read identifier codes operation outputs the manufacturer code, device code and the block lock configuration codes for each block (see Figure 5 on page 10). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. The block lock configuration codes identify locked and unlocked blocks.
3.7
Write
Writing commands to the CUI enables reading of device data, query, identifier codes, inspection and clearing of the status register, and, when VPEN = VPENH, block erasure, program, and lock-bit configuration. The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte/Word Program command requires the command and address of the location to be written. Set Block Lock-Bit commands require the command and block within the device to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location. It is written when the device is enabled and WE# is active. The address and data needed to execute a command are latched on the rising edge of WE# or the first edge of CE0, CE1, or CE2 that disables the device (see Table 2). Standard microprocessor write timings are used.
4.0
Command Definitions
When the VPEN voltage VPENLK, only read operations from the status register, query, identifier codes, or blocks are enabled. Placing VPENH on VPEN additionally enables block erase, program, and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 4 defines these commands.
Preliminary
9
28F128J3A, 28F640J3A, 28F320J3A
Figure 5. Device Identifier Code Memory Map
Word Address 7FFFFF A[23-1]: 128 Mbit A[22-1]: 64 Mbit A[21-1]: 32 Mbit Block 127 Reserved for Future Implementation Block 127 Lock Configuration Reserved for Future Implementation (Blocks 64 through 126) Block 63 Reserved for Future Implementation Block 63 Lock Configuration Reserved for Future Implementation (Blocks 32 through 62) Block 31 Reserved for Future Implementation 1F0003 1F0002 Block 31 Lock Configuration 64 Mbit 32 Mbit Reserved for Future Implementation (Blocks 2 through 30) Block 1 Reserved for Future Implementation Block 1 Lock Configuration Reserved for Future Implementation Block 0 Reserved for Future Implementation
7F0003 7F0002
7F0000 7EFFFF 3FFFFF
3F0003 3F0002
3F0000 3EFFFF
1F0000 1EFFFF 01FFFF
010003 010002
010000 00FFFF
000004 000003 000002 000001 000000 Block 0 Lock Configuration Device Code Manufacturer Code
128 Mbit
0606-06a
NOTE: A0 is not used in either x8 or x16 modes when obtaining these identifier codes. Data is always given on the low byte in
x16 mode (upper byte contains 00h).
10
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Table 3.
Mode Read Array Output Disable Standby
Bus Operations
Notes 4,5,6 RP# VIH VIH VIH VIL VIH VIH VIH VIH 6,10,11 VIH CE0,1,2(1) Enabled Enabled Disabled X Enabled Enabled Enabled Enabled Enabled OE#(2) VIL VIH X X VIL VIL VIL VIL VIH WE#(2) VIH VIH X X VIH VIH VIH VIH VIL Address X X X X See Figure 5 See Table 7 X X X VPEN X X X X X X X X VPENH DQ(3) DOUT High Z High Z High Z Note 8 Note 9 DOUT DQ7 = DOUT DQ15-8 = High Z DQ6-0 = High Z DIN X STS (default mode) High Z(7) X X High Z(7) High Z(7) High Z(7)
Reset/Power-Down Mode Read Identifier Codes Read Query Read Status (WSM off) Read Status (WSM on) Write
NOTES: 1. See Table 2 for valid CE configurations. 2. OE# and WE# should never be enabled simultaneously. 3. DQ refers to DQ0-DQ7 if BYTE# is low and DQ0-DQ15 if BYTE# is high. 4. Refer to DC Characteristics. When VPEN VPENLK, memory contents can be read, but not altered. 5. X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN. See DC Characteristics for VPENLK and VPENH voltages. 6. In default mode, STS is VOL when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It is VOH when the WSM is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or reset/power-down mode. 7. High Z will be VOH with an external pull-up resistor. 8. See Section 3.6 for read identifier code data. 9. See Section 4.2 for read query data. 10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN = VPENH and VCC is within specification. 11. Refer to Table 4 for valid DIN during a write operation.
Preliminary
11
28F128J3A, 28F640J3A, 28F320J3A
Table 4.
Command
Intel(R) StrataFlashTM Memory Command Set Definitions(1)
Scalable or Basic Command Set(2) Bus Cycles Req'd. Notes First Bus Cycle Second Bus Cycle
Oper(3) Read Array Read Identifier Codes Read Query Read Status Register Clear Status Register Write to Buffer SCS/BCS SCS/BCS SCS SCS/BCS SCS/BCS SCS/BCS 1 2 2 2 1 >2 9, 10, 11 12,13 11,12 12,14 12 8 7 Write Write Write Write Write Write
Addr(4) X X X X X BA
Data(5,6) FFH 90H 98H 70H 50H E8H 40H or 10H 20H B0H D0H B8H 60H 60H C0H
Oper(3)
Addr(4)
Data(5,6)
Read Read Read
IA QA X
ID QD SRD
Write
BA
N
Word/Byte Program Block Erase Block Erase, Program Suspend Block Erase, Program Resume Configuration Set Block Lock-Bit Clear Block Lock-Bits Protection Program
SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS SCS SCS
2 2 1 1 2 2 2 2
Write Write Write Write Write Write
X BA X X X X X X
Write Write
PA BA
PD D0H
Write Write Write Write
X BA X PA
CC 01H D0H PD
15
Write Write
NOTES: 1. Commands other than those shown above are reserved by Intel for future device implementations and should not be used. 2. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scalable Command Set (SCS) is also referred to as the Intel Extended Command Set. 3. Bus operations are defined in Table 3. 4. X = Any valid address within the device. BA = Address within the block. IA = Identifier Code Address: see Figure 5 and Table 15. QA = Query database Address. PA = Address of memory location to be programmed. RCD = Data to be written to the read configuration register. This data is presented to the device on A16-1; all other address inputs are ignored. 5. ID = Data read from Identifier Codes. QD = Data read from Query database. SRD = Data read from status register. See Table 16 for a description of the status register bits. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#. CC = Configuration Code. 6. The upper byte of the data bus (DQ8-DQ15) during command writes is a "Don't Care" in x16 operation. 7. Following the Read Identifier Codes command, read operations access manufacturer, device and block lock codes. See Section 4.3 for read identifier code data. 8. If the WSM is running, only DQ7 is valid; DQ15-DQ8 and DQ6-DQ0 float, which places them in a highimpedance state. 9. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.
12
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
10.The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument. Count ranges on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N = 000FH. The third and consecutive bus cycles, as determined by N, are for writing data into the Write Buffer. The Confirm command (D0H) is expected after exactly N + 1 write cycles; any other command at that point in the sequence aborts the write to buffer operation. Please see Figure 7, "Write to Buffer Flowchart" on page 30 for additional information. 11. The write to buffer or erase operation does not begin until a Confirm command (D0h) is issued. 12.Attempts to issue a block erase or program to a locked block. 13.Either 40H or 10H are recognized by the WSM as the byte/word program setup. 14.Program suspends can be issued after either the Write-to-Buffer or Word-/Byte-Program operation is initiated. 15.The clear block lock-bits operation simultaneously clears all block lock-bits.
4.1
Read Array Command
Upon initial device power-up and after exit from reset/power-down mode, the device defaults to read array mode. The read configuration register defaults to asynchronous read page mode. The Read Array command also causes the device to enter read array mode. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, program, or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase or Program Suspend command. The Read Array command functions independently of the VPEN voltage.
4.2
Read Query Mode Command
This section defines the data structure or "database" returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI.
4.2.1
Query Structure Output
The Query "database" allows system software to gain information for controlling the flash component. This section describes the device's CFI-compliant interface that allows the host system to access Query data. Query data are always presented on the lowest-order data outputs (DQ0-7) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two bytes of the Query structure, "Q" and "R" in ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H data on upper bytes. Thus, the device outputs ASCII "Q" in the low byte (DQ0-7) and 00h in the high byte (DQ8-15). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address.
Preliminary
13
28F128J3A, 28F640J3A, 28F320J3A
In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. In addition, since the upper byte of word-wide devices is always "00h," the leading "00" has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode. Table 5. Summary of Query Structure Output as a Function of Device and Mode
Device Type/ Mode Query start location in maximum device bus width addresses Query data with maximum device bus width addressing Hex Offset x16 device x16 mode x16 device x8 mode 10h 10: 11: 12: Hex Code 0051 0052 0059 N/A(1) ASCII Value "Q" "R" "Y" Query data with byte addressing Hex Offset 20: 21: 22: 20: 21: 22: Hex Code 51 00 52 51 51 52 ASCII Value "Q" "Null" "R" "Q" "Q" "R"
N/A(1)
NOTE: 1. The system must drive the lowest order addresses to access all the device's array data when the device is configured in x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the system, is "Not Applicable" for x8-configured devices.
Table 6.
Example of Query Structure Output of a x16- and x8-Capable Device
Word Addressing Offset A15-A0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h ... 0051 0052 0059 P_IDLO P_IDHI PLO PHI A_IDLO A_IDHI ... Hex Code D15-D0 "Q" "R" "Y" PrVendor ID # PrVendor TblAdr AltVendor ID # ... Value Offset A7-A0 20h 21h 22h 23h 24h 25h 26h 27h 28h ... 51 51 52 52 59 59 P_IDLO P_IDLO P_IDHI ... Byte Addressing Hex Code D7-D0 "Q" "Q" "R" "R" "Y" "Y" PrVendor ID # ID # ... Value
4.2.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database." The structure sub-sections and address locations are summarized below. See AP-646 Common Flash Interface (CFI) and Command Sets (order number 292204) for a full description of CFI. The following sections describe the Query structure sub-sections in detail.
14
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Table 7.
Query Structure(1)
Offset 00h 01h (BA+2)h(2) 04-0Fh 10h 1Bh 27h P(3) Block Status Register Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table Sub-Section Name Manufacturer Code Device Code Block-Specific Information Reserved for Vendor-Specific Information Reserved for Vendor-Specific Information Command Set ID and Vendor Data Offset Flash Device Layout Vendor-Defined Additional Information Specific to the Primary Vendor Algorithm Description
NOTES: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = Block Address beginning location (i.e., 02000h is block 2's beginning location when the block size is 128 Kbyte). 3. Offset 15 defines "P" which points to the Primary Intel-Specific Extended Query Table.
4.2.3
Block Status Register
The block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations.
Table 8.
Block Status Register
Offset (BA+2)h
(1)
Length 1
Description Block Lock Status Register BSR.0 Block Lock Status 0 = Unlocked 1 = Locked BSR 1-7: Reserved for Future Use
Address BA+2: BA+2: BA+2:
Value --00 or --01 (bit 0): 0 or 1 (bit 1-7): 0
NOTE: 1. BA = The beginning location of a Block Address (i.e., 008000h is block 1's (64-KB block) beginning location in word mode).
4.2.4
CFI Query Identification String
The CFI Query Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s).
Table 9.
CFI Identification
Offset Length Description Add. 10 11: 12: 13: 14: 15: 16: Hex Code --51 --52 --59 --01 --00 --31 --00 Value "Q" "R" "Y"
10h 13h 15h
3 2 2
Query-unique ASCII string "QRY" Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms Extended Query Table primary algorithm address
Preliminary
15
28F128J3A, 28F640J3A, 28F320J3A
Table 9.
CFI Identification
Offset 17h 19h Length 2 2 Description Alternate vendor command set and control interface ID code. 0000h means no second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists Add. 17: 18: 19: 1A: Hex Code --00 --00 --00 --00 Value
4.2.5
System Interface Information
The following device information can optimize system interface software.
Table 10. System Interface Information
Offset 1Bh Length 1 Description VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts "n" such that typical single word program time-out = 2n s "n" such that typical max. buffer write time-out = 2n s "n" such that typical block erase time-out = 2n ms "n" such that typical full chip erase time-out = 2n ms "n" such that maximum word program time-out = 2n times typical "n" such that maximum buffer write time-out = 2n times typical "n" such that maximum block erase time-out = 2n times typical "n" such that maximum chip erase time-out = 2n times typical Add. 1B: Hex Code --27 Value 2.7 V
1Ch
1
1C:
--36
3.6 V
1Dh
1
1D:
--00
0.0 V
1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
1 1 1 1 1 1 1 1 1
1E: 1F: 20: 21: 22: 23: 24: 25: 26:
--00 --07 --07 --0A --00 --04 --04 --04 --00
0.0 V 128 s 128 s 1s NA 2 ms 2 ms 16 s NA
16
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
4.2.6
Device Geometry Definition
This field provides critical details of the flash device geometry.
Table 11. Device Geometry Definition
Offset 27h 28h 2Ah Length 1 2 2 Description "n" such that device size = 2n in number of bytes Flash device interface: x8 async x16 async x8/x16 async 28:00,29:00 28:01,29:00 28:02,29:00 "n" such that maximum number of bytes in write buffer = 2n Number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in "bulk" 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks 3. Symmetrically blocked partitions have one blocking region 4. Partition size = (total blocks) x (individual block size) Erase Block Region 1 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes Code See Table Below 27: 28: 29: 2A: 2B: --02 --00 --05 --00 x8/ x16 32
2Ch
1
2C:
--01
1
2Dh
4
2D: 2E: 2F: 30:
Device Geometry Definition
Address 27: 28: 29: 2A: 2B: 2C: 2D: 2E: 2F: 30: 32 Mbit --16 --02 --00 --05 --00 --01 --1F --00 --00 --02 64 Mbit --17 --02 --00 --05 --00 --01 --3F --00 --00 --02 128 Mbit --18 --02 --00 --05 --00 --01 --7F --00 --00 --02
Preliminary
17
28F128J3A, 28F640J3A, 28F320J3A
4.2.7
Primary-Vendor Specific Extended Query Table
Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query table specifies this and other similar information.
Table 12. Primary Vendor-Specific Extended Query
Offset(1) P = 31h (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h Length 3 Description (Optional Flash Features and Commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature and command support (1=yes, 0=no) bits 9-31 are reserved; undefined bits are "0." If bit 31 is "1" then another 31 bit field of optional features follows at the end of the bit-30 field. bit 0 Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock/unlock supported bit 4 Queued erase supported bit 5 Instant Individual block locking supported bit 6 Protection bits supported bit 7 Page-mode read supported bit 8 Synchronous read supported Supported functions after suspend: read Array, Status, Query Other supported operations are: bits 1-7 reserved; undefined bits are "0" bit 0 Program supported after erase suspend Block status register mask bits 2-15 are Reserved; undefined bits are "0" bit 0 Block Lock-Bit Status register active bit 1 Block Lock-Down Bit Status active VCC logic supply highest performance program/erase voltage bits 0-3 BCD value in 100 mV bits 4-7 BCD value in volts VPP optimum program/erase supply voltage bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts Add. Hex Code Value "P" "R" "I" "1" "1"
1 1
(P+5)h (P+6)h (P+7)h (P+8)h
4
31: --50 32: --52 33: --49 34: --31 35: --31 36: --0A 37: --00 38: --00 39: --00 bit 0 = 0 bit 1 = 1 bit 2 = 1 bit 3 = 1(1) bit 4 = 0 bit 5 = 0 bit 6 = 1 bit 7 = 1 bit 8 = 0 3A: --01
No Yes Yes Yes(1) No No Yes Yes No
(P+9)h
1
(P+A)h (P+B)h
2
bit 0 = 1 3B: --01 3C: --00 bit 0 = 1 bit 1 = 0 3D: --33
Yes
Yes No 3.3 V
(P+C)h
1
(P+D)h
1
3E:
--00
0.0 V
NOTE: 1. Future devices may not support the described "Legacy Lock/Unlock" function. Thus bit 3 would have a value of "0."
18
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Table 13. Protection Register Information
Offset(1) P = 31h (P+E)h Length 1 Description (Optional Flash Features and Commands) Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection bytes are available Protection Field 1: Protection Description This field describes user-available One Time Programmable (OTP) protection register bytes. Some are pre-programmed with device-unique serial numbers. Others are userprogrammable. Bits 0-15 point to the protection register lock byte, the section's first byte. The following bytes are factory pre-programmed and user-programmable. bits 0-7 = Lock/bytes JEDEC-plane physical low address bits 8-15 = Lock/bytes JEDEC-plane physical high address bits 16-23 = "n" such that 2n = factory pre-programmed bytes bits 24-31 = "n" such that 2n = user-programmable bytes Add. 3F: Hex Code --01 Value 01
(P+F)h (P+10)h (P+11)h (P+12)h
4
40:
--00
00h
NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h.
Table 14. Burst Read Information
Offset(1) P = 31h Length Description (Optional Flash Features and Commands) Page Mode Read capability (P+13)h 1 bits 0-7 = "n" such that 2n HEX value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. Reserved for future use 44: --03 8 byte Add. Hex Code Value
(P+14)h (P+15)h
1
45: 46:
--00
0
NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h.
4.3
Read Identifier Codes Command
The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Figure 5 on page 10 retrieve the manufacturer, device and block lock configuration codes (see Table 15 for identifier code values). Page-mode reads are not supported in this read mode. To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the VPEN voltage. This command is valid only when the WSM is off or the device is suspended. Following the Read Identifier Codes command, the following information can be read:
Preliminary
19
28F128J3A, 28F640J3A, 28F320J3A
Table 15. Identifier Codes
Code Manufacture Code Device Code 32-Mbit 64-Mbit 128-Mbit Block Lock Configuration * Block Is Unlocked * Block Is Locked * Reserved for Future Use Address(1) 00000 00001 00001 00001
X0002(2)
Data (00) 89 (00) 16 (00) 17 (00) 18 DQ0 = 0 DQ0 = 1 DQ1-7
NOTES: 1. A0 is not used in either x8 or x16 modes when obtaining the identifier codes. The lowest order address line is A1. Data is always presented on the low byte in x16 mode (upper byte contains 00h). 2. X selects the specific block's lock configuration code. See Figure 5 for the device identifier code memory map.
4.4
Read Status Register Command
The status register may be read to determine when a block erase, program, or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. Page-mode reads are not supported in this read mode. The status register contents are latched on the falling edge of OE# or the first edge of CE0, CE1, or CE2 that enables the device (see Table 2, "Chip Enable Truth Table" on page 7). OE# must toggle to VIH or the device must be disabled (see Table 2) before further reads to update the status register latch. The Read Status Register command functions independently of the VPEN voltage. During a program, block erase, set lock-bit, or clear lock-bit command sequence, only SR.7 is valid until the Write State Machine completes or suspends the operation. Device I/O pins DQ0-DQ6 and DQ8-DQ15 are placed in a high-impedance state. When the operation completes or suspends (check status register bit 7), all contents of the status register are valid when read.
20
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Table 16. Status Register Definitions
WSMS bit 7 High Z When Busy? No Yes ESS bit 6 ECLBS bit 5 PSLBS bit 4 VPENS bit 3 PSS bit2 DPS bit 1 R bit 0
Status Register Bits SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR LOCK-BITSSTATUS 1 = Error in Block Erasure or Clear Lock-Bits 0 = Successful Block Erase or Clear Lock-Bits SR.4 = PROGRAM AND SET LOCK-BIT STATUS 1 = Error in Setting Lock-Bit 0 = Successful Set Block Lock Bit SR.3 = PROGRAMMING VOLTAGE STATUS 1 = Low Programming Voltage Detected, Operation Aborted 0 = Programming Voltage OK SR.2 = PROGRAM SUSPEND STATUS 1 = Program suspended 0 = Program in progress/completed SR.1 = DEVICE PROTECT STATUS 1 = Block Lock-Bit Detected, Operation Abort 0 = Unlock
Notes Check STS or SR.7 to determine block erase, program, or lock-bit configuration completion. SR.6- SR.0 are not driven while SR.7 = "0."
Yes Yes Yes
If both SR.5 and SR.4 are "1"s after a block erase or lock-bit configuration attempt, an improper command sequence was entered.
Yes
SR.3 does not provide a continuous programming voltage level indication. The WSM interrogates and indicates the programming voltage level only after Block Erase, Program, Set Block Lock-Bit, or Clear Block Lock-Bits command sequences.
Yes
SR.1 does not provide a continuous indication of block lock-bit values. The WSM interrogates the block lock-bits only after Block Erase, Program, or Lock-Bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set. Read the block lock configuration codes using the Read Identifier Codes command to determine block lock-bit status. SR.0 is reserved for future use and should be masked when polling the status register.
Yes
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
Table 17. eXtended Status Register Definitions
WBS bit 7 High Z When Busy? No Yes Reserved bits 6--0
Status Register Bits
Notes After a Buffer-Write command, XSR.7 = 1 indicates that a Write Buffer is available. SR.6-SR.0 are reserved for future use and should be masked when polling the status register.
XSR.7 = WRITE BUFFER STATUS 1 = Write buffer available 0 = Write buffer not available XSR.6-XSR.0 = RESERVED FOR FUTURE ENHANCEMENTS
Preliminary
21
28F128J3A, 28F640J3A, 28F320J3A
4.5
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 16). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VPEN voltage. The Clear Status Register command is only valid when the WSM is off or the device is suspended.
4.6
Block Erase Command
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires an appropriate address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 10, "Block Erase Flowchart" on page 33). The CPU can detect block erase completion by analyzing the output of the STS pin or status register bit SR.7. Toggle OE#, CE0, CE1, or CE2 to update the status register. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1." Also, reliable block erasure can only occur when VCC is valid and VPEN = VPENH. If block erase is attempted while VPEN VPENLK, SR.3 and SR.5 will be set to "1." Successful block erase requires that the corresponding block lock-bit be cleared. If block erase is attempted when the corresponding block lock-bit is set, SR.1 and SR.5 will be set to "1."
4.7
Block Erase Suspend Command
The Block Erase Suspend command allows block-erase interruption to read or program data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bit SR.7 then SR.6 can determine when the block erase operation has been suspended (both will be set to "1"). In default mode, STS will also transition to VOH. Specification tWHRH defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A program command sequence can also be issued during erase suspend to program data in other blocks. During a program operation with block erase suspended, status register bit SR.7 will return to "0" and STS output (in default mode) will transition to VOL. However, SR.6 will remain "1" to indicate block erase suspend status. Using the Program Suspend command, a program operation can also be suspended. Resuming a suspended programming operation by
22
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
issuing the Program Resume command allows continuing of the suspended programming operation. To resume the suspended erase, the user must wait for the programming operation to complete before issuing the Block Erase Resume command. The only other valid commands while block erase is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and STS (in default mode) will return to VOL. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 11, "Block Erase Suspend/Resume Flowchart" on page 34). VPEN must remain at VPENH (the same VPEN level used for block erase) while block erase is suspended. Block erase cannot resume until program operations initiated during block erase suspend have completed.
4.8
Write to Buffer Command
To program the flash device, a Write to Buffer command sequence is initiated. A variable number of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. First, the Write to Buffer Setup command is issued along with the Block Address (see Figure 7, "Write to Buffer Flowchart" on page 30). At this point, the eXtended Status Register (XSR, see Table 17) information is loaded and XSR.7 reverts to "buffer available" status. If XSR.7 = 0, the write buffer is not available. To retry, continue monitoring XSR.7 by issuing the Write to Buffer setup command with the Block Address until XSR.7 = 1. When XSR.7 transitions to a "1," the buffer is ready for loading. Now a word/byte count is given to the part with the Block Address. On the next write, a device start address is given along with the write buffer data. Subsequent writes provide additional device addresses and data, depending on the count. All subsequent addresses must lie within the start address plus the count. Internally, this device programs many flash cells in parallel. Because of this parallel programming, maximum programming performance and lower power are obtained by aligning the start address at the beginning of a write buffer boundary (i.e., A4-A0 of the start address = 0). After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM (Write State Machine) to begin copying the buffer data to the flash array. If a command other than Write Confirm is written to the device, an "Invalid Command/Sequence" error will be generated and Status Register bits SR.5 and SR.4 will be set to a "1." For additional buffer writes, issue another Write to Buffer Setup command and check XSR.7. If an error occurs while writing, the device will stop writing, and status register bit SR.4 will be set to a "1" to indicate a program failure. The internal WSM verify only detects errors for "1"s that do not successfully program to "0"s. If a program error is detected, the status register should be cleared. Any time SR.4 and/or SR.5 is set (e.g., a media failure occurs during a program or an erase), the device will not accept any more Write to Buffer commands. Additionally, if the user attempts to program past an erase block boundary with a Write to Buffer command, the device will abort the write to buffer operation. This will generate an "Invalid Command/Sequence" error and status register bits SR.5 and SR.4 will be set to a "1." Reliable buffered writes can only occur when VPEN = VPENH. If a buffered write is attempted while VPEN VPENLK, status register bits SR.4 and SR.3 will be set to "1." Buffered write attempts with invalid VCC and VPEN voltages produce spurious results and should not be attempted. Finally, successful programming requires that the corresponding block lock-bit be reset. If a buffered write is attempted when the corresponding block lock-bit is set, SR.1 and SR.4 will be set to "1."
Preliminary
23
28F128J3A, 28F640J3A, 28F320J3A
4.9
Byte/Word Program Commands
Byte/Word program is executed by a two-cycle command sequence. Byte/Word program setup (standard 40H or alternate 10H) is written followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the program and program verify algorithms internally. After the program sequence is written, the device automatically outputs status register data when read (see Figure 8, "Byte/Word Program Flowchart" on page 31). The CPU can detect the completion of the program event by analyzing the STS pin or status register bit SR.7. When program is complete, status register bit SR.4 should be checked. If a program error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully program to "0"s. The CUI remains in read status register mode until it receives another command. Reliable byte/word programs can only occur when VCC and VPEN are valid. If a byte/word program is attempted while VPEN VPENLK, status register bits SR.4 and SR.3 will be set to "1." Successful byte/word programs require that the corresponding block lock-bit be cleared. If a byte/ word program is attempted when the corresponding block lock-bit is set, SR.1 and SR.4 will be set to "1."
4.10
Program Suspend Command
The Program Suspend command allows program interruption to read data in other flash memory locations. Once the programming process starts (either by initiating a write to buffer or byte/word program operation), writing the Program Suspend command requests that the WSM suspend the program sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Program Suspend command is written. Polling status register bits SR.7 can determine when the programming operation has been suspended. When SR.7 = 1, SR.2 should also be set to "1", indicating that the device is in the program suspend mode. STS in level RY/BY# mode will also transition to VOH. Specification tWHRH1 defines the program suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while programming is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Program Resume. After a Program Resume command is written, the WSM will continue the programming process. Status register bits SR.2 and SR.7 will automatically clear and STS in RY/BY# mode will return to VOL. After the Program Resume command is written, the device automatically outputs status register data when read. VPEN must remain at VPENH and VCC must remain at valid VCC levels (the same VPEN and VCC levels used for programming) while in program suspend mode. Refer to Figure 9, "Program Suspend/Resume Flowchart" on page 32.
4.11
Set Read Configuration Command
This command is not support on this product. This device will default to the asynchronous page mode. If this command is given to the device it will not effect the operation of the device.
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Preliminary
28F128J3A, 28F640J3A, 28F320J3A
4.11.1
Read Configuration
The device will support both asynchronous page mode and standard word/byte reads. No configuration is required. Status register and identifier only support standard word/byte single read operations.
Table 18. Read Configuration Register Definition
RM 16 (A16) R 8 R 15 R 7 R 14 R 6 R 13 R 5 R 12 R 4 R 11 R 3 Notes RCR.16 = READ MODE (RM) 0 = Standard Word/Byte Reads Enabled (Default) 1 = Page-Mode Reads Enabled RCR.15-1 = RESERVED FOR FUTURE ENHANCEMENTS (R) Read mode configuration effects reads from the flash array. Status register, query, and identifier reads support standard word/byte read cycles. These bits are reserved for future use. Set these bits to "0." R 10 R 2 R 9 R 1
4.12
Configuration Command
The Status (STS) pin can be configured to different states using the Configuration command. Once the STS pin has been configured, it remains in that configuration until another configuration command is issued or RP# is asserted low. Initially, the STS pin defaults to RY/BY# operation where RY/BY# low indicates that the state machine is busy. RY/BY# high indicates that the state machine is ready for a new operation or suspended. Table 19, "Configuration Coding Definitions" on page 26 displays the possible STS configurations. To reconfigure the Status (STS) pin to other modes, the Configuration command is given followed by the desired configuration code. The three alternate configurations are all pulse mode for use as a system interrupt as described below. For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 00h configuration code with the Configuration command resets the STS pin to the default RY/BY# level mode. The possible configurations and their usage are described in Table 19, "Configuration Coding Definitions" on page 26. The Configuration command may only be given when the device is not busy or suspended. Check SR.7 for device status. An invalid configuration code will result in both status register bits SR.4 and SR.5 being set to "1." When configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.
Preliminary
25
28F128J3A, 28F640J3A, 28F320J3A
Table 19. Configuration Coding Definitions
Pulse on Program Complete(1) bit 1 DQ7-DQ2 are reserved for future use. default (DQ1-DQ0 = 00) RY/BY#, level mode -- used to control HOLD to a memory controller to prevent accessing a flash memory subsystem while any flash device's WSM is busy. configuration 01 ER INT, pulse mode -- used to generate a system interrupt pulse when any flash device in an array has completed a Block Erase. Helpful for reformatting blocks after file system free space reclamation or "cleanup" configuration 10 PR INT, pulse mode -- used to generate a system interrupt pulse when any flash device in an array has complete a Program operation. Provides highest performance for servicing continuous buffer write operations. configuration 11 ER/PR INT, pulse mode -- used to generate system interrupts to trigger servicing of flash arrays when either erase or program operations are completed when a common interrupt service routine is desired. Pulse on Erase Compete(1) bit 0
Reserved
bits 7--2 DQ7-DQ2 = Reserved DQ1-DQ0 = STS Pin Configuration Codes 00 = default, level mode RY/BY# (device ready) indication 01 = pulse on Erase complete 10 = pulse on Program complete 11 = pulse on Erase or Program Complete Configuration Codes 01b, 10b, and 11b are all pulse mode such that the STS pin pulses low then high when the operation indicated by the given configuration is completed. Configuration Command Sequences for STS pin configuration (masking bits DQ7-DQ2 to 00h) are as follows: Default RY/BY# level mode: B8h, 00h ER INT (Erase Interrupt): B8h, 01h Pulse-on-Erase Complete PR INT (Program Interrupt): B8h, 02h Pulse-on-Program Complete ER/PR INT (Erase or Program Interrupt): B8h, 03h Pulse-on-Erase or Program Complete
NOTE: 1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.
4.13
Set Block Lock-Bit Commands
A flexible block locking and unlocking scheme is enabled via block lock-bits. The block lock-bits gate program and erase operations. Individual block lock-bits can be set using the Set Block LockBit command. This command is invalid while the WSM is running or the device is suspended. Set block lock-bit commands are executed by a two-cycle sequence. The set block setup along with appropriate block address is followed by either the set block lock-bit confirm (and an address within the block to be locked). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Figure 12 on page 35). The CPU can detect the completion of the set lock-bit event by analyzing the STS pin output or status register bit SR.7. When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block Lock-Bit command will result in status register bits SR.4 and SR.5 being set to "1." Also, reliable operations occur only when VCC and VPEN are valid. With VPEN VPENLK, lock-bit contents are protected against alteration.
26
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
4.14
Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. Block lockbits can be cleared using only the Clear Block Lock-Bits command. This command is invalid while the WSM is running or the device is suspended. Clear block lock-bits command is executed by a two-cycle sequence. A clear block lock-bits setup is first written. The device automatically outputs status register data when read (see Figure 13 on page 36). The CPU can detect completion of the clear block lock-bits event by analyzing the STS pin output or status register bit SR.7. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status register bits SR.4 and SR.5 being set to "1." Also, a reliable clear block lock-bits operation can only occur when VCC and VPEN are valid. If a clear block lock-bits operation is attempted while VPEN VPENLK, SR.3 and SR.5 will be set to "1." If a clear block lock-bits operation is aborted due to VPEN or VCC transitioning out of valid range, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values.
4.15
Protection Register Program Command
The 3 Volt Intel StrataFlash memory includes a 128-bit protection register that can be used to increase the security of a system design. For example, the number contained in the protection register can be used to "mate" the flash component with other system components such as the CPU or ASIC, preventing device substitution. The 128-bits of the protection register are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other segment is left blank for customer designers to program as desired. Once the customer segment is programmed, it can be locked to prevent reprogramming.
4.15.1
Reading the Protection Register
The protection register is read in the identification read mode. The device is switched to this mode by writing the Read Identifier command (90H). Once in this mode, read cycles from addresses shown in Table 20 or Table 21 retrieve the specified information. To return to read array mode, write the Read Array command (FFH).
4.15.2
Programming the Protection Register
The protection register bits are programmed using the two-cycle Protection Program command. The 64-bit number is programmed 16 bits at a time for word-wide parts and eight bits at a time for byte-wide parts. First write the Protection Program Setup command, C0H. The next write to the
Preliminary
27
28F128J3A, 28F640J3A, 28F320J3A
device will latch in address and data and program the specified location. The allowable addresses are shown in Table 20 or Table 21. See Figure 14, "Protection Register Programming Flowchart" on page 37 Any attempt to address Protection Program commands outside the defined protection register address space will result in a status register error (program error bit SR.4 will be set to 1). Attempting to program a locked protection register segment will result in a status register error (program error bit SR.4 and lock error bit SR.1 will be set to 1).
4.15.3
Locking the Protection Register
The user-programmable segment of the protection register is lockable by programming Bit 1 of the PR-LOCK location to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique device number. Bit 1 is set using the Protection Program command to program "FFFD" to the PR-LOCK location. After these bits have been programmed, no further changes can be made to the values stored in the protection register. Protection Program commands to a locked section will result in a status register error (program error bit SR.4 and Lock Error bit SR.1 will be set to 1). Protection register lockout state is not reversible.
Figure 6. Protection Register Memory Map
Word Address 88H
A[23 - 1]: 128 Mbit A[22 - 1]: 64 Mbit A[21 - 1]: 32 Mbit
4 Words User Programmed 85H 84H 4 Words Factory Programmed 81H 80H 1 Word Lock
0667_06
NOTE: A0 is not used in x16 mode when accessing the protection register map (See Table 20 for x16 addressing). For x8 mode A0 is used (See Table 21 for x8 addressing).
28
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Table 20. Word-Wide Protection Register Addressing
Word LOCK 0 1 2 3 4 5 6 7 Use Both Factory Factory Factory Factory User User User User A8 1 1 1 1 1 1 1 1 1 A7 0 0 0 0 0 0 0 0 0 A6 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 1 A3 0 0 0 0 1 1 1 1 0 A2 0 0 1 1 0 0 1 1 0 A1 0 1 0 1 0 1 0 1 0
NOTE: 1. All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A23-A9 = 0.
Table 21. Byte-Wide Protection Register Addressing
Byte LOCK LOCK 0 1 2 3 4 5 6 7 8 9 A B C D E F Use Both Both Factory Factory Factory Factory Factory Factory Factory Factory User User User User User User User User A8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
NOTE: 1. All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A23-A9 = 0.
Preliminary
29
28F128J3A, 28F640J3A, 28F320J3A
Figure 7. Write to Buffer Flowchart
Start Set Time-Out Issue Write to Buffer Command E8H, Block Address Read Extended Status Register No Bus Operation Write Read Command Write to Buffer Comments Data = E8H Block Address XSR. 7 = Valid Addr = Block Address Check XSR. 7 1 = Write Buffer Available 0 = Write Buffer Not Available Data = N = Word/Byte Count N = 0 Corresponds to Count = 1 Addr = Block Address Data = Write Buffer Data Addr = Device Start Address Data = Write Buffer Data Addr = Device Address Program Buffer Data = D0H to Flash Addr = Block Address Confirm Status Register Data with the Device Enabled, OE# Low Updates SR Addr = Block Address Check SR.7 1 = WSM Ready 0 = WSM Busy
Standby
XSR.7 = 1 Write Word or Byte Count, Block Address Write Buffer Data, Start Address X=0 Yes Check X = N? No Abort Write to Buffer Command? Yes No Write Next Buffer Data, Device Address X=X+1 Program Buffer to Flash Confirm D0H
0
Write to Buffer Time-Out?
Write (Note 1, 2) Write (Note 3, 4) Write (Note 5, 6) Write
Read (Note 7)
Standby Yes Yes Write to Another Block Address
Write to Buffer Aborted
1. Byte or word count values on DQ - DQ7 are loaded into the 0 count register. Count ranges on this device for byte mode are N = 00H to 1FH and for word mode are N = 0000H to 000FH. 2. The device now outputs the status register when read (XSR is no longer available). 3. Write Buffer contents will be programmed at the device start address or destination flash address. 4. Align the start address on a Write Buffer boundary for maximum programming performance (i.e., A - A0 of the start 4 address = 0). 5. The device aborts the Write to Buffer command if the current address is outside of the original block address. 6. The status register indicates an "improper command sequence" if the Write to Buffer command is aborted. Follow this with a Clear Status Register command. 7. Toggling OE# (low to high to low) updates the status register. This can be done in place of issuing the Read Status Register command. Full status check can be done after all erase and write sequences complete. Write FFH after the last operation to reset the device to read array mode.
Another Write to Buffer? No Read Status Register 1 0 SR.7 = 1 Full Status Check if Desired Programming Complete Issue Read Status Command
0606_07A
30
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure 8. Byte/Word Program Flowchart
Start
Bus Operation Write Write
Command Setup Byte/ Word Program Byte/Word Program
Comments Data = 40H Addr = Location to Be Programmed Data = Data to Be Programmed Addr = Location to Be Programmed Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 40H, Address Write Data and Address Read Status Register 0 1 Full Status Check if Desired Byte/Word Program Complete
Read (Note 1) Standby
SR.7 =
1. Toggling OE# (low to high to low) updates the status register. This can be done in place of issuing the Read Status Register command. Repeat for subsequent programming operations. SR full status check can be done after each program operation, or after a sequence of programming operations. Write FFH after the last program operation to place device in read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.1 = 0 1 SR.4 = 0 Byte/Word Program Successful Programming Error Voltage Range Error
Standby Bus Operation Standby Command Comments Check SR.3 1 = Programming to Voltage Error Detect Check SR.1 1 = Device Protect Detect RP# = VIH, Block Lock-Bit Is Set Only required for systems implemeting lock-bit configuration. Check SR.4 1 = Programming Error
1 Device Protect Error
Standby
Toggling OE# (low to high to low) updates the status register. This can be done in place of issuing the Read Status Register command. Repeat for subsequent programming operations. SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are programmed before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
Preliminary
31
28F128J3A, 28F640J3A, 28F320J3A
Figure 9. Program Suspend/Resume Flowchart
Bus Operation Write Write B0H Read
Start
Command Program Suspend
Comments Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 - WSM Ready 0 = WSM Busy Check SR.6 1 = Programming Suspended 0 = Programming Completed
Read Status Register
Standby
0 SR.7 =
Standby
Write 1 0 SR.2 = Programming Completed Write 1 Write FFH Read
Read Array
Data = FFH Addr = X Read array locations other than that being programmed.
Program Resume
Data = D0H Addr = X
Read Data Array
No Done Reading Yes Write D0H Write FFH
Programming Resumed
Read Array Data
0606_08
32
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure 10. Block Erase Flowchart
Bus Operation Write Issue Single Block Erase Command 20H, Block Address Write (Note 1)
Start
Command Erase Block Erase Confirm
Comments Data = 20H Addr = Block Address Data = D0H Addr = X Status register data With the device enabled, OE# low updates SR Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy
Read
Standby Write Confirm D0H Block Address
1. The Erase Confirm byte must follow Erase Setup. This device does not support erase queuing. Please see Application note AP-646 For software erase queuing compatibility. Full status check can be done after all erase and write sequences complete. Write FFH after the last operation to reset the device to read array mode. Suspend Erase Loop
Read Status Register No
SR.7 =
0
Suspend Erase
Yes
1 Full Status Check if Desired
Erase Flash Block(s) Complete
0606_09
Preliminary
33
28F128J3A, 28F640J3A, 28F320J3A
Figure 11. Block Erase Suspend/Resume Flowchart
Bus Operation Write Write B0H Read
Start
Command Erase Suspend
Comments Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 - WSM Ready 0 = WSM Busy Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed
Read Status Register
Standby
0 SR.7 =
Standby
Write 1 0 SR.6 = Block Erase Completed
Erase Resume
Data = D0H Addr = X
1 Read Read or Program? Read Array Data Done? Yes Write D0H Write FFH Program Loop Program
No
Block Erase Resumed
Read Array Data
0606_10
34
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure 12. Set Block Lock-Bit Flowchart
Start
Bus Operation Write
Command Set Block Lock-Bit Setup Set Block Lock-Bit Confirm
Comments Data = 60H Addr =Block Address Data = 01H Addr = Block Address Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 60H, Block Address Write 01H, Block Address
Write
Read
Read Status Register
Standby
SR.7 = 1 Full Status Check if Desired
0
Repeat for subsequent lock-bit operations. Full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. Write FFH after the last lock-bit set operation to place device in read array mode.
Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 1 SR.4,5 = 0 1 SR.4 = 0 Set Lock-Bit Successful
0606_11b
Bus Operation Standby
Command
Comments Check SR.3 1 = Programming Voltage Error Detect Check SR.4, 5 Both 1 = Command Sequence Error Check SR.4 1 = Set Lock-Bit Error
Voltage Range Error
Standby
Command Sequence Error
Standby
Set Lock-Bit Error
SR.5, SR.4 and SR.3 are only cleared by the Clear Status Register command, in cases where multiple lock-bits are set before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
Preliminary
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28F128J3A, 28F640J3A, 28F320J3A
Figure 13. Clear Lock-Bit Flowchart
Start
Bus Operation Write
Command Clear Block Lock-Bits Setup Clear Block or Lock-Bits Confirm
Comments Data = 60H Addr = X Data = D0H Addr = X Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 60H
Write
Write D0H
Read
Read Status Register
Standby
SR.7 = 1 Full Status Check if Desired Clear Block Lock-Bits Complete
0
Write FFH after the clear lock-bits operation to place device in read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 1 SR.4,5 = 0 1 SR.5 = 0 Clear Block Lock-Bits Successful
0606_12b
Bus Operation Standby
Command
Comments Check SR.3 1 = Programming Voltage Error Detect Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Clear Block Lock-Bits Error
Voltage Range Error
Standby
Command Sequence Error
Standby
SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register command.
Clear Block Lock-Bits Error
If an error is detected, clear the status register before attempting retry or other error recovery.
36
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure 14. Protection Register Programming Flowchart
Start
Bus Operation Write Write
Command Protection Program Setup Protection Program
Comments Data = C0H Data = Data to Program Addr = Location to Program Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write C0H (Protection Reg. Program Setup) Write Protect. Register Address/Data
Read
Standby
Read Status Register
SR.7 = 1? Yes Full Status Check if Desired
No
Protection Program operations can only be addressed within the protection register address space. Addresses outside the defined space will return an error. Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of program operations. Write FFH after the last program operation to reset device to read array mode.
Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1, 1 SR.3, SR.4 = VPEN Range Error 0,1 SR.1, SR.4 =
Standby Bus Operation Standby Command Comments SR.1 SR.3 SR.4 0 1 1 VPEN Low 0 0 1 Prot. Reg. Prog. Error Register Locked: Aborted
1
0
1
Protection Register Programming Error Attempted Program to Locked Register Aborted
Standby
SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine.
1,1 SR.1, SR.4 =
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases of multiple protection register program operations before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
Program Successful
Preliminary
37
28F128J3A, 28F640J3A, 28F320J3A
5.0
5.1
Design Considerations
Three-Line Output Control
The device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1, CE2, OE#, and RP#) to accommodate multiple memory connections. This control provides for:
a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur.
To use these control inputs efficiently, an address decoder should enable the device (see Table 2) while OE# should be connected to all memory devices and the system's READ# control line. This assures that only selected memory devices have active outputs while de-selected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.
5.2
STS and Block Erase, Program, and Lock-Bit Configuration Polling
STS is an open drain output that should be connected to VCCQ by a pull-up resistor to provide a hardware method of detecting block erase, program, and lock-bit configuration completion. It is recommended that a 2.5k resister be used between STS# and VCCQ. In default mode, it transitions low after block erase, program, or lock-bit configuration commands and returns to High Z when the WSM has finished executing the internal algorithm. For alternate configurations of the STS pin, see the Configuration command. STS can be connected to an interrupt input of the system CPU or controller. It is active at all times. STS, in default mode, is also High Z when the device is in block erase suspend (with programming inactive), program suspend, or in reset/power-down mode.
5.3
Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE0, CE1, CE2, and OE#. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Since Intel StrataFlash memory devices draw their power from three VCC pins (these devices do not include a VPP pin), it is recommended that systems without separate power and ground planes attach a 0.1 F ceramic capacitor between each of the device's three VCC pins (this includes VCCQ) and ground. These high-frequency, low-inductance capacitors should be placed as close as possible to package leads on each Intel StrataFlash memory device. Each device should have a 0.1 F ceramic capacitor connected between its VCC and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 F electrolytic capacitor should be placed between VCC and GND at the array's power supply connection. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance.
38
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
5.4
Input Signal Transitions - Reducing Overshoots and Undershoots When Using Buffers or Transceivers
As faster, high-drive devices such as transceivers or buffers drive input signals to flash memory devices, overshoots and undershoots can sometimes cause input signals to exceed flash memory specifications. (See "Absolute Maximum Ratings" on page 40.) Many buffer/transceiver vendors now carry bus-interface devices with internal output-damping resistors or reduced-drive outputs. Internal output-damping resistors diminish the nominal output drive currents, while still leaving sufficient drive capability for most applications. These internal output-damping resistors help reduce unnecessary overshoots and undershoots. Transceivers or buffers with balanced- or lightdrive outputs also reduce overshoots and undershoots by diminishing output-drive currents. When considering a buffer/transceiver interface design to flash, devices with internal output-damping resistors or reduced-drive outputs should be used to minimize overshoots and undershoots. For additional information, please refer to the AP-647 5 Volt Intel StrataFlashTM Memory Design Guide.
5.5
VCC, VPEN, RP# Transitions
Block erase, program, and lock-bit configuration are not guaranteed if VPEN or VCC falls outside of the specified operating ranges, or RP# VIH. If RP# transitions to VIL during block erase, program, or lock-bit configuration, STS (in default mode) will remain low for a maximum time of tPLPH + tPHRH until the reset operation is complete. Then, the operation will abort and the device will enter reset/power-down mode. The aborted operation may leave data partially corrupted after programming, or partially altered after an erase or lock-bit configuration. Therefore, block erase and lock-bit configuration commands must be repeated after normal operation is restored. Device power-off or RP# = VIL clears the status register. The CUI latches commands issued by system software and is not altered by VPEN, CE0, CE1, or CE2 transitions, or WSM actions. Its state is read array mode upon power-up, after exit from reset/ power-down mode, or after VCC transitions below VLKO. VCC must be kept at or above VPEN during VCC transitions. After block erase, program, or lock-bit configuration, even after VPEN transitions down to VPENLK, the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. VPEN must be kept at or below VCC during VPEN transitions.
5.6
Power-Up/Down Protection
The device is designed to offer protection against accidental block erasure, programming, or lockbit configuration during power transitions. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for VCC voltages above VLKO when VPEN is active. Since WE# must be low and the device enabled (see Table 2) for a command write, driving WE# to VIH or disabling the device will inhibit writes. The CUI's two-step command sequence architecture provides added protection against data alteration. Keeping VPEN below VPENLK prevents inadvertent data alteration. In-system block lock and unlock capability protects the device against inadvertent programming. The device is disabled while RP# = VIL regardless of its control inputs.
Preliminary
39
28F128J3A, 28F640J3A, 28F320J3A
5.7
Power Dissipation
When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory's nonvolatility increases usable battery life because data is retained when system power is removed.
6.0
6.1
Electrical Specifications
Absolute Maximum Ratings
Parameter Temperature under Bias Expanded Storage Temperature Voltage On Any Pin Output Short Circuit Current Maximum Rating -25 C to +85 C -65 C to +125 C -2.0 V to +5.0 V(1) 100 mA(2)
NOTES: 1. All specified voltages are with respect to GND. Minimum DC voltage is -0.5 V on input/output pins and -0.2 V on VCC and VPEN pins. During transitions, this level may undershoot to -2.0 V for periods <20 ns. Maximum DC voltage on input/output pins, VCC, and VPEN is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns. 2. Output shorted for no more than one second. No more than one output shorted at a time.
NOTICE: This datasheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design.
Warning:
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
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Preliminary
28F128J3A, 28F640J3A, 28F320J3A
6.2
Operating Conditions
Table 22. Temperature and VCC Operating Conditions
Symbol TA VCC1 VCC2 VCCQ1 VCCQ2 Parameter Operating Temperature VCC1 Supply Voltage (2.7 V-3.6 V) VCC2 Supply Voltage (3.0 V-3.6 V) VCCQ1 Supply Voltage (2.7 V-3.6 V) VCCQ2 Supply Voltage (3.0 V-3.6 V) Notes Min -25 2.70 3.00 2.70 3.00 Max +85 3.60 3.60 3.60 3.60 Unit C V V V V Test Condition Ambient Temperature
6.3
Capacitance
TA = +25 C, f = 1 MHz
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Typ 6 8 Max 8 12 Unit pF pF Condition VIN = 0.0 V VOUT = 0.0 V
NOTES: 1. Sampled, not 100% tested.
Preliminary
41
28F128J3A, 28F640J3A, 28F320J3A
6.4
Symbol ILI ILO ILO
DC Characteristics
Parameter Input and VPEN Load Current Output Leakage Current Output Leakage Current Notes 1 1 1 Typ Max 1 10 10 Unit A A A Test Conditions VCC = VCC Max; VCCQ = VCCQ Max VIN = VCCQ or GND VCC = VCC Max; VCCQ = VCCQ Max VIN = VCCQ or GND VCC = VCC Max; VCCQ = VCCQ Max VIN = VCCQ or GND CMOS Inputs, VCC = VCC Max, Device is enabled (see Table 2, "Chip Enable Truth Table" on page 7), RP# = VCCQ 0.2 V TTL Inputs, VCC = VCC Max, Device is enabled (see Table 2), RP# = VIH RP# = GND 0.2 V, IOUT (STS) = 0 mA CMOS Inputs, VCC = VCC Max, VCCQ = VCCQ Max using standard 4 word page mode reads. Device is enabled (see Table 2) f = 5 MHz, IOUT = 0 mA CMOS Inputs,VCC = VCC Max, VCCQ = VCCQ Max using standard 4 word page mode reads. Device is enabled (see Table 2) f = 33 MHz, IOUT = 0 mA CMOS Inputs, VCC = VCC Max, VCCQ = VCCQ Max using standard word/byte single reads Device is enabled (see Table 2) f = 5 MHz, IOUT = 0 mA
50 ICCS VCC Standby Current 1,2,3,4 0.71 ICCD VCC Power-Down Current 4 50
120
A
2 120
mA A
15 ICCR VCC Page Mode Read Current 1,3,4 24
20
mA
29
mA
ICCR
VCC Byte Mode Read Current
1,3,4
40
50
mA
ICCW
VCC Program or Set Lock-Bit Current VCC Block Erase or Clear Block Lock-Bits Current VCC Program Suspend or Block Erase Suspend Current
35 1,4,5 40 35 1,4,5 40 1,4,6
60 70 70 80 10
mA mA mA mA mA
CMOS Inputs, VPEN = VCC TTL Inputs, VPEN = VCC CMOS Inputs, VPEN = VCC TTL Inputs, VPEN = VCC Device is disabled (see Table 2)
ICCE ICCWS ICCES
42
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
DC Characteristics, Continued
Symbol VIL VIH Parameter Input Low Voltage Input High Voltage Notes 5 5 Min -0.5 2.0 Max 0.8 VCCQ + 0.5 0.4 VOL Output Low Voltage 2,5 0.2 0.85 x VCCQ VCCQ - 0.2 VPENLK VPENH VLKO VPEN Lockout during Program, Erase and Lock-Bit Operations VPEN during Block Erase, Program, or Lock-Bit Operations VCC Lockout Voltage 5,7,8 7,8 9 2.7 2.0 2.0 3.6 V V V V V V Unit V V V VCCQ = VCCQ2/3 Min IOL = 2 mA VCCQ = VCCQ2/3 Min IOL = 100 A VCCQ = VCCQ Min IOH = -2.5 mA VCCQ = VCCQ Min IOH = -100 A Test Conditions
VOH
Output High Voltage
2,5
NOTES: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact Intel's Application Support Hotline or your local sales office for information about typical specifications. 2. Includes STS. 3. CMOS inputs are either VCC 0.2 V or GND 0.2 V. TTL inputs are either VIL or VIH. 4. Current values are specified over the temperature range (0 C to 70 C) and may increase slightly at -25 C. 5. Sampled, not 100% tested. 6. ICCWS and ICCES are specified with the device de-selected. If the device is read or written while in erase suspend mode, the device's current draw is ICCR or ICCW. 7. Block erases, programming, and lock-bit configurations are inhibited when VPEN VPENLK, and not guaranteed in the range between VPENLK (max) and VPENH (min), and above VPENH (max). 8. Typically, VPEN is connected to VCC (2.7 V-3.6 V). 9. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO, and not guaranteed in the range between VLKO (min) and VCC (min), and above VCC (max).
Figure 15. Transient Input/Output Reference Waveform for VCCQ = 3.0 V-3.6 V or VCCQ = 2.7 V-3.6 V
VCCQ Input 0.0 VCCQ/2 Test Points VCCQ/2 Output
NOTE: AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.
Preliminary
43
28F128J3A, 28F640J3A, 28F320J3A
Figure 16. Transient Equivalent Testing Load Circuit
1.3V 1N914 RL = 3.3 k Device Under Test Out CL
NOTE: CL Includes Jig Capacitance Test Configuration VCCQ = VCC = 3.0 V-3.6 V VCCQ = VCC = 2.7 V-3.6 V CL (pF) 30 30
44
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
6.5
AC Characteristics-- Read-Only Operations(1,2)
VCC VCCQ Notes 32 Mbit 3.0 V-3.6 V (3) 3.0 V-3.6 V (3) Min 110 120 150 110 120 150 2 2 2 2, 4 32 Mbit 110 120 150 50 150 180 210 5 5 5 5 5 5 0 10 1000 5 5 5, 6 4 0 25 25 1000 0 30 30 0 0 55 15 0 10 1000 1000 0 0 55 15 Max 2.7 V-3.6 V (3) 2.7 V-3.6 V (3) Min 110 120 150 110 120 150 110 120 150 50 150 180 210 Max
Versions (All units in ns unless otherwise noted) # Sym Parameter
R1
tAVAV
Read/Write Cycle Time
64 Mbit 128 Mbit 32 Mbit
R2
tAVQV
Address to Output Delay
64 Mbit 128 Mbit 32 Mbit
R3
tELQV
CEX to Output Delay
64 Mbit 128 Mbit
R4
tGLQV
OE# to Non-Array Output Delay
R5
tPHQV
RP# High to Output Delay
64 Mbit 128 Mbit
R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
tELQX tGLQX tEHQZ tGHQZ tOH tELFL/tELFH tFLQV/tFHQV tFLQZ tEHEL tAPA tGLQV
CEX to Output in Low Z OE# to Output in Low Z CEX High to Output in High Z OE# High to Output in High Z Output Hold from Address, CEX, or OE# Change, Whichever Occurs First CEX Low to BYTE# High or Low BYTE# to Output Delay BYTE# to Output in High Z CEx High to CEx Low Page Address Access Time OE# to Array Output Delay NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 2).
1. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate. 2. OE# may be delayed up to tELQV-tGLQV after the first edge of CE0, CE1, or CE2 that enables the device (see Table 2) without impact on tELQV. 3. See Figures 14-16, Transient Input/Output Reference Waveform for VCCQ = 3.0 V -3.6 V or VCCQ = 2.7 V - 3.6 V, and Transient Equivalent Testing Load Circuit for testing characteristics. 4. When reading the flash array a faster tGLQV (R16) applies. Non-array reads refer to status register reads, query reads, or device identifier reads. 5. Sampled, not 100% tested. 6. For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV).
Preliminary
45
28F128J3A, 28F640J3A, 28F320J3A
Figure 17. AC Waveform for Both Page-Mode and Standard Word/Byte Read Operations
VIH
ADDRESSES [A23-A3]
VIL VIH Valid Address
R1 Valid Valid Address Address Valid Address R14
ADDRESSES [A2-A0]
VIL
Disabled (VIH)
CEX [E]
Enabled (VIL) R2 R8 VIH VIL R3 R4 or R16 R5 High Z R6 Valid Output R7 R15 Valid Output Valid Output Valid Output R10 High Z R9
OE# [G]
WE# [W]
VIH VIL
DATA [D/Q] VOH DQ0-DQ15
VOL VIH VIL VIH
VCC
RP# [P]
VIL VIH
R11
R12 R13
BYTE# [F]
VIL
0606_16
NOTE: CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 2). For standard word/byte read operations, R15 (tAPA) will equal R2 (tAVQV). When reading the flash array a faster tGLQV (R16) applies. Non-array reads refer to status register reads, query reads, or device identifier reads.
46
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
6.6
AC Characteristics-- Write Operations(1,2)
Valid for All Speeds Notes 3 4 4 5 5 Min 1 0 70 50 55 10 0 0 6 3 7 8 3,8,9 0 30 0 35 500 Max s ns ns ns ns ns ns ns ns ns ns ns ns
Versions # W1 W2 W3 W4 W5 W6 W7 W8 W9 W11 W12 W13 W15 Symbol tPHWL (tPHEL) tELWL (tWLEL) tWP tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWPH tVPWH (tVPEH) tWHGL (tEHGL) tWHRL (tEHRL) tQVVL NOTES: Parameter RP# High Recovery to WE# (CEX) Going Low CEX (WE#) Low to WE# (CEX) Going Low Write Pulse Width Data Setup to WE# (CEX) Going High Address Setup to WE# (CEX) Going High CEX (WE#) Hold from WE# (CEX) High Data Hold from WE# (CEX) High Address Hold from WE# (CEX) High Write Pulse Width High VPEN Setup to WE# (CEX) Going High Write Recovery before Read WE# (CEX) High to STS Going Low VPEN Hold from Valid SRD, STS Going High
Unit
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 2).
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics-Read-Only Operations. 2. A write operation can be initiated and terminated with either CEX or WE#. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low first) to CEX or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. If CEX is driven low 10 ns before WE# going low, WE# pulse width requirement decreases to tWP - 10 ns. 5. Refer to Table 4 for valid AIN and DIN for block erase, program, or lock-bit configuration. 6. Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write. 8. STS timings are based on STS configured in its RY/BY# default mode. 9. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0).
Preliminary
47
28F128J3A, 28F640J3A, 28F320J3A
6.7
Block Erase, Program, and Lock-Bit Configuration Performance(1,2,3)
# W16 W16 tWHQV3 tEHQV3 Sym Parameter Write Buffer Byte Program Time (Time to Program 32 bytes/16 words) Byte Program Time (Using Word/Byte Program Command) Block Program Time (Using Write to Buffer Command) W16 W16 W16 W16 W16 tWHQV4 tEHQV4 tWHQV5 tEHQV5 tWHQV6 tEHQV6 tWHRH1 tEHRH1 tWHRH tEHRH Block Erase Time Set Lock-Bit Time Clear Block Lock-Bits Time Program Suspend Latency Time to Read Erase Suspend Latency Time to Read Notes 4,5,6,7 4 4 4 4 4 Typ 218 210 0.8 1.0 64 0.5 25 26 Max 654 630 2.4 5.0 75 0.70 75 35 Unit s s sec sec s sec s s
NOTES: 1. Typical values measured at TA = +25 C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. These performance numbers are valid for all speed versions. 3. Sampled but not 100% tested. 4. Excludes system-level overhead. 5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary. 6. Effective per-byte program time (tWHQV1, tEHQV1) is 6.8 s/byte (typical) 7. Effective per-word program time (tWHQV2, tEHQV2) is 13.6 s/word (typical) 8. Max values are measured at worst case temperature and VCC corner after 100k cycles
48
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure 18. AC Waveform for Write Operations
A VIH VIL Disabled (VIH) CEX, (WE#) [E(W)] Enabled (VIL) VIH OE# [G] VIL
W2 W1
B
C
D
E
F
ADDRESSES [A]
AIN W5
AIN W8
W6
W12
W9
W16
Disabled (VIH) WE#, (CEX) [W(E)] Enabled (VIL)
W4
W3 W7 DIN DIN W13 Valid SRD DIN High Z
VIH DATA [D/Q] VIL VOH STS [R] VOL VIH VIL
RP# [P]
W11
W15
VPENH VPENLK VPEN [V] VIL
0606_17
NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 2). STS is shown in its default mode (RY/BY#).
a. b. c. d. e. f.
VCC power-up and standby. Write block erase, write buffer, or program setup. Write block erase or write buffer confirm, or valid address and data. Automated erase delay. Read status register or query data. Write Read Array command.
Preliminary
49
28F128J3A, 28F640J3A, 28F320J3A
Figure 19. AC Waveform for Reset Operation
STS (R)
VIH VIL
P2
RP# (P)
VIH VIL
P1
0606_18
NOTE: STS is shown in its default mode (RY/BY#).
Reset Specifications(1)
# P1 Sym tPLPH tPHRH Parameter RP# Pulse Low Time (If RP# is tied to VCC, this specification is not applicable) RP# High to Reset during Block Erase, Program, or Lock-Bit Configuration Notes 2 Min 35 Max Unit s
P2
3
100
ns
NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum required RP# Pulse Low Time is 100 ns. 3. A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid.
50
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
7.0
Ordering Information
RC2 8 F 1 2 8 J 3 A - 1 5 0
Package E = 56-Lead TSOP RC = 64-Ball Easy BGA Access Speed (ns)1 128 Mbit = 150 64 Mbit = 120 32 Mbit = 110 Intel(R) 0.25 micron ETOXTM VI Process Technology Voltage (VCC/VPEN) 3 = 3 V/3 V Product Family J = Intel(R) StrataFlashTM memory, 2 bits-per-cell
Product line designator for all Intel(R) Flash products Device Density 128 = x8/x16 (128 Mbit) 640 = x8/x16 (64 Mbit) 320 = x8/x16 (32 Mbit)
NOTE: 1. These speeds are for either the standard asynchronous read access times or for the first access of a pagemode read sequence.
VALID COMBINATIONS
56-Lead TSOP E28F128J3A-150 E28F640J3A-120 E28F320J3A-110 64-Ball Easy BGA RC28F128J3A-150 RC28F640J3A-120 RC28F320J3A-110
Preliminary
51
28F128J3A, 28F640J3A, 28F320J3A
8.0
Additional Information
Order Number 298130 290668 292237 Note 3 290606 290608 290609 290429 290598 290597 297859 292222 292221 292218 292205 292204 292202 298161 Note 4
Document/Tool 3 Volt Intel(R) StrataFlashTM Memory 28F128J3A, 28F640J3A, 320J3A Specification Update Intel(R) Persistent Storage Manager datasheet AP-689 Using Intel(R) Persistent Storage Manager AP-707 3 Volt Intel(R) StrataFlashTM Memory CPU Interface Design Guide 5 Volt Intel(R) StrataFlashTM MemoryI28F320J5 and 28F640J5 datasheet 3 Volt FlashFileTM Memory; 28F160S3 and 28F320S3 datasheet 5 Volt FlashFileTM Memory; 28F160S5 and 28F320S5 datasheet 5 Volt FlashFileTM Memory; 28F008SA datasheet 3 Volt FlashFileTM Memory; 28F004S3, 28F008S3, 28F016S3 datasheet 5 Volt FlashFileTM Memory; 28F004S5, 28F008S5, 28F016S5 datasheet AP-677 Intel(R) StrataFlashTM Memory Technology AP-664 Designing Intel(R) StrataFlashTM Memory into Intel(R) Architecture AP-663 Using the Intel(R) StrataFlashTM Memory Write Buffer AP-660 Migration Guide to 3 Volt Intel(R) StrataFlashTM Memory AP-647 5 Volt Intel(R) StrataFlashTM Memory Design Guide AP-646 Common Flash Interface (CFI) and Command Sets AP-644 Migration Guide to 5 Volt Intel(R) StrataFlashTM Memory Intel(R) Flash Memory Chip Scale Package User's Guide Preliminary Mechanical Specification for Easy BGA Package
NOTE: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.intel.com for technical documentation and tools. 3. For the most current information on Intel StrataFlash memory, visit our website at http://developer.intel.com/ design/flash/isf. 4. This document is available on the web at http://developer.intel.com/design/flcomp/packdata/298049.htm.
52
Preliminary

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